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1 * this specification are subject to be changed without notice. EM78P154A/b 8-bit micro-controller for general purpose product 9.30.1997 general description the EM78P154A/b is an 8-bit microprocessor with low-power, high speed cmos technology. there are 0.64kx13 bits electrical one time programmable read only memory (otp-rom) within it. it provides 13 security bits and 6 one-time programmable option bits to protect the otp memory code from any external access as well as the user's options. the otp rom will be incorporated into EM78P154A/b 8-bit microcontroller instead of it's original memory. the user's development program can be easily programmed into or verify from this otp memory by using emc otp writer. features ? operating voltage range : 2.5v ~ 6.5v ? available in temperature range: ? operation speed : dc ~ 36 mhz ? low power consumption : * <2ma, at 5v/4mhz *15 m a typical, at 3v/32khz *1 m a typical, at sleep ? 0.64k x 13 electrical programmable read only memory (otp-rom) ? one security register is provided to protect the otp memory code and to define user's id code. ? one configuration register is provided to meet the user's options. ? 14 special function registers. ? 48 x 8 on chip ram. ? 2 bi-directional tri-state i/o ports (12 i/o pins). ? 5 level stack for subroutine nesting. ? 8-bit real time clock/counter (tcc) with selective signal sources and trigger edges, and with overflow interrupt. ? programmable free running on-chip watchdog timer. ? two r-option pin. ? power down mode. ? input port change interrupt (wake-up), and external interrupt available. ? 99.9% single instruction cycle commands. ? 18 pin dip, 18 pin soic, 20 pin ssop. ? power on voltage detector. ? EM78P154A : enabled ? em78p154b : disabled ? function compatiable with em78156 except otp memory inside. EM78P154A/b 8-bit micro-controller for general purpose product
* this specification are subject to be changed without notice. EM78P154A/b 8-bit micro-controller for general purpose product 2 9.30.1997 pin descriptions symbol i/o function osci i xtal type : crystal input terminal or external clock input pin. rc type: rc oscillator input pin. osco i/o xtal type: output terminal for crystal oscillator or external clock input pin. rc type: clock output with a period of one instruction cycle is put on this pin. tcc i real time clock/counter, schmitt trigger input pin. must be tied to v dd or v ss if not in use. reset i schmitt trigger input pin. if this pin remains logic low, the controller is reset. p50~p53 i/o p50~p53 are bi-directional i/o ports. p50 and p51 are also the r-option pins. p50~p52 can be pulled-down by software control. functional block diagram pin assignments otp 1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10 EM78P154Ap/bp p52 p53 tcc reset v ss p60,int p61 p62 p63 1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10 p51 p50 osci osco v dd p67 p66 p65 p64 EM78P154Am/bm soic dip p52 p53 tcc reset v ss v ss p60,int p61 p62 p63 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 p51 p50 osci osco v dd v dd p67 p66 p65 p64 EM78P154As/bs ssop p52 p53 tcc reset v ss p60,int p61 p62 p63 p51 p50 osci osco v dd p67 p66 p65 p64
3 * this specification are subject to be changed without notice. EM78P154A/b 8-bit micro-controller for general purpose product 9.30.1997 symbol i/o function p60~p67 i/o p60~p67 are bi-directional i/o ports. they can be pulled-high internally by software control and can have open-drain output by software control. in addition, p60~p63 can be pulled-down by software control. int i falling edge triggered, external interrupt input pin. it is the secondary function of p60. v dd - power supply pin. v ss - ground pin. function descriptions operational registers r0 (indirect addressing register) ? r0 is not a physically implemented register. it is useful as indirect addressing pointer. any instruction using r0 as register actually accesses data pointed by the ram select register (r4). r1 (tcc) ? increased by an external signal edge applied to tcc pin, or by the instruction cycle clock. ? written and read by the program as any other register. r2 (program counter) & stack ? generates 0.64k x 13 on-chip otp rom addresses to the relative programming instruction codes. one program page is 0.64k words long. ? r2 is set all "0"s upon s reset condition. ? "jmp" instruction allows the direct loading of the lower 10 program counter bits. thus, "jmp" allows jump to any location on one page. ? "call" instruction loads the lower 10 bits of the pc, and then pc+1 is pushed into the stack. thus, the subroutine entry address can be any location on one page. ? "ret" ("retl k", "reti") instruction loads the program counter with the contents at the top of stack. ? "add r2,a" allows a relative address be added to the current pc, and contents of the ninth and tenth bits of pc are cleared. ? "mov r2,a" allows the loading of an address from the "a" register to the lower 8 bits of pc, and the ninth and tenth bits of pc are cleared. ? any instruction which writes to r2 (e.g. "add r2,a", "mov r2,a", "bc r2,6",....) will cause the ninth and tenth bits (a8~a9) of pc to be cleared. thus, the computed jump is limited to the first 256 locations of any program page. ? all instructions are single instruction cycle except that the instructions which write to r2 need one more instruction cycle.
* this specification are subject to be changed without notice. EM78P154A/b 8-bit micro-controller for general purpose product 4 9.30.1997 fig. 4 data memory configuration fig. 3 program counter organization cont a9 a8 a7~a0 10 bits jmp mov r2,a a9=a8=0 add r2, a a9=a8=0 10 bits 10 bits 8 bits call, ret reti retlk stack 1 stack 5 ~
5 * this specification are subject to be changed without notice. EM78P154A/b 8-bit micro-controller for general purpose product 9.30.1997 r3 (status register) 7 6 543210 gp2 gp1 gp0 t p z dc c bit 0 (c) carry flag bit 1 (dc) auxiliary carry flag bit 2 (z) zero flag. set to "1" if the result of an arithmetic or logic operation is zero. bit 3 (p) power down bit. set to 1 during power on or by a wdtc command and reset to 0 by a slep command. bit 4 (t) time-out bit. set to 1 by the slep and wdtc command, or during power up and reset to 0 by wdt timeout. bit 5~7 (gp0~2) general purpose read/write bit. r4 (ram select register) ? bits 0 ~ 5 are used to select registers (address: 00~06, 0f~3f) in the indirect addressing mode. ? if no indirect addressing is used, the rsr can be used as an 6-bit wide general purpose read/write register. ? bits 6 ~ 7 are general register. ? see the configuration of the data memory in fig. 4. r5 ~ r6 (port 5 ~ port 6) ? r5 and r6 are i/o registers. ? only low order 4 bits are used in r5. rf (interrupt status register) 7 6 5 4 32 10 - - - - - exif icif tcif ? "1" means interrupt request, "0" means non-interrupt bit 0 (tcif) tcc timer overflow interrupt flag. set when tcc timer overflows, reset in software. bit 1 (icif) port 6 input change interrupt flag. set when port 6 input changes, reset in software. bit 2 (exif) external interrupt flag. set by falling edge on /int pin, reset in software. bits 3 ~ 7 not used. ? rf can be cleared by instruction and cannot be set by instruction. ? iocf is the interrupt mask register. ? note that reading rf by instruction will get the result of "logic and" of rf and iocf. r10 ~ r3f ? r10 ~ r3f are the 48x8 general purpose registers. special purpose registers a (accumulator)
* this specification are subject to be changed without notice. EM78P154A/b 8-bit micro-controller for general purpose product 6 9.30.1997 ? internal data transfer, or instruction operand holding ? its not an addressable register. cont (control register) 76 543 21 0 - int ts te pab psr2 psr1 psr0 bit 0 (psr0) tcc/wdt prescaler bits. bit 2 (psr2) psr2 psr1 psr0 tcc rate wdt rate 0 0 0 1:2 1:1 0 0 1 1:4 1:2 0 1 0 1:8 1:4 0 1 1 1:16 1:8 1 0 0 1:32 1:16 1 0 1 1:64 1:32 1 1 0 1:128 1:64 1 1 1 1:256 1:128 ~ bit 3 (pab) prescaler assignment bit. 0: tcc 1: wdt bit 4 (te) tcc signal edge 0: increment from low to high transition on tcc pin 1: increment from high to low transition on tcc pin bit 5 (ts) tcc signal source 0: internal instruction cycle clock 1: transition on tcc pin bit 6 (int) int enable flag 0: interrupt masked by disi or hardware interrupt 1: interrupt enabled by eni/reti instructions bit 7 not used. ? cont register is readable and writable. ioc5 ~ ioc6 (i/o port control register) ? "1" put the relative i/o pin into high impedance, while "0" put the relative i/o pin as output. ? low order 4 bits are used in ioc5. ? ioc5 and ioc6 registers are readable and writable. iocb (pull-down control register) 76543210 /pd7 /pd6 /pd5 /pd4 - /pd2 /pd1 /pd0
7 * this specification are subject to be changed without notice. EM78P154A/b 8-bit micro-controller for general purpose product 9.30.1997 bit 0 (/pd0) control bit used to enable the pull-down of p50 pin. 0: enable internal pull-down 1: disable internal pull-down bit 1 (/pd1) control bit used to enable the pull-down of p51 pin. bit 2 (/pd2) control bit used to enable the pull-down of p52 pin. bit 3 not used. bit 4 (/pd4) control bit used to enable the pull-down of p60 pin. bit 5 (/pd5) control bit used to enable the pull-down of p61 pin. bit 6 (/pd6) control bit used to enable the pull-down of p62 pin. bit 7 (/pd7) control bit used to enable the pull-down of p63 pin. ? iocb register is readable and writable. iocc (open-drain control register) 76543210 od7 od6 od5 od4 od3 od2 od1 od0 bit 0 (od0) control bit used to enable the open-drain of p60 pin. 0: disable open-drain output 1: enable open-drain output bit 1 (od1) control bit used to enable the open-drain of p61 pin. bit 2 (od2) control bit used to enable the open-drain of p62 pin. bit 3 (od3) control bit used to enable the open-drain of p63 pin. bit 4 (od4) control bit used to enable the open-drain of p64 pin. bit 5 (od5) control bit used to enable the open-drain of p65 pin. bit 6 (od6) control bit used to enable the open-drain of p66 pin. bit 7 (od7) control bit used to enable the open-drain of p67 pin. ? iocc register is readable and writable. iocd (pull-high control register) 7 6 5 4 3210 /ph7 /ph6 /ph5 /ph4 /ph3 /ph2 /ph1 /ph0 bit 0 (/ph0) control bit used to enable the pull-high of p60 pin. 0: enable internal pull-high 1: disable internal pull-high bit 1 (/ph1) control bit used to enable the pull-high of p61 pin. bit 2 (/ph2) control bit used to enable the pull-high of p62 pin. bit 3 (/ph3) control bit used to enable the pull-high of p63 pin. bit 4 (/ph4) control bit used to enable the pull-high of p64 pin. bit 5 (/ph5) control bit used to enable the pull-high of p65 pin. bit 6 (/ph6) control bit used to enable the pull-high of p66 pin. bit 7 (/ph7) control bit used to enable the pull-high of p67 pin. ? iocd register is readable and writable. ioce (wdt control register)
* this specification are subject to be changed without notice. EM78P154A/b 8-bit micro-controller for general purpose product 8 9.30.1997 76543210 wdte eis - roc - - - - bit 7 (wdte) control bit used to enable watchdog timer. 0: disable wdt 1: enable wdt wdte bit is readable and writable. bit 6 (eis) control bit used to select the function of p60(/int) pin. 0: p60, bidirectional i/o pin. 1: /int, external interrupt input pin. in this case, the i/o control bit of p60 (bit 0 of ioc6) must be set to "1". when eis is 0, the path of /int is masked. when eis is "1", the status of /int pin can also be read by port 6(r6). refer to fig. 7(a). eis bit is readable and writable. bit 4 (roc) roc is used for the r-option. setting roc to 1 will enable the status of r-option pins (p50~p51) to be read by the controller. clearing roc will disable the r-option function. if the r-option function is used, the user must connect the p51 pin or/and p50 pin to vss by a 430k w external resistir (rex). if rex is connected/disconnected, the status of p50(p51) will be read as "0"/"1" when roc is set to "1". refer to fig. 8. roc bit is readable and writable. bits 0 ~ 3, 5 not used. iocf (interrupt mask register) 7 6 5 4 3210 - - - - - exie icie tcie bit 0 (tcie) tcif interrupt enable bit. 0: disable tcif interrupt 1: enable tcif interrupt bit 1 (icie) icif interrupt enable bit. 0: disable icif interrupt 1: enable icif interrupt bit 2 (exie) exif interrupt enable bit. 0: disable exif interrupt 1: enable exif interrupt bits 3 ~ 7 not used. ? individual interrupt is enabled by setting its associated control bit in iocf to "1". ? global interrupt is enabled by eni instruction and is disabled by disi instruction. refer to fig.10. ? iocf register is readable and writable. tcc/wdt & prescaler there is an 8-bit counter available as prescaler for the tcc or wdt. the prescaler is available for the tcc only or wdt only at the same time and the pab bit of cont register is used to determine the prescaler assignment. the psr0~psr2 bits determine the prescale ratio. fig. 5 depicts the circuit diagram of tcc/wdt. r1(tcc) is an 8-bit timer/counter. the clock source of tcc can be internal clock or external clock input (edge selectable from tcc pin). tcc will increase by 1 every instruction cycle (without prescaler). the prescaler will be cleared by instructions which write to tcc each time, when assigned to tcc mode. the watchdog timer is a free running on-chip rc oscillator. the wdt will keep running even the oscillator driver has been turned off (i.e. in sleep mode). during the normal operation or the sleep mode, wdt time-out
9 * this specification are subject to be changed without notice. EM78P154A/b 8-bit micro-controller for general purpose product 9.30.1997 (if enabled) will cause the device to reset. the wdt can be enabled or disabled at any time during the normal mode by software programming. refer to wdte bit ioce register. with no presacler, the wdt time-out period is approximately 18 ms. the wdt and prescaler, when assigned to wdt mode, will be cleared by the wdtc and clep instructions. i/o ports the i/o registers, port 5~port 6, are bi-directional tri-state i/o ports. port 6 can be pulled-high internally by software control. in addition, port 6 can also have open-drain output by software control. there are input change interrupt (or wake-up) function on port 6. p50~p52 and p60~p63 pins can be pulled-down by sodtware control. each i/o pins can be defined as "input" or "output" pins by the i/o control register (ioc5~ioc6) under program control. p50~p51 are the r-option pins which are enabled by software. while r-option function is used, p50~p51 are recommed as input pins. if external resistor is connected to p50(p51) for r-option function, the current consumption should be noticed in the applications that low power are concerned. the i/o registers and i/o control registers are both readable and writable. the i/o interface circuits for port 5 and port 6 are shown in fig. 6 and fig. 7(a), (b) respectively. fig. 5 block diagram of tcc and wdt data bus 8-bit counter 8-to-1 mux tcc overflow interrupt psr0 ~psr2 wdt timeout wdte (in ioce) tcc pin te pab mux ts pab pab 1 0 0 1 1 0 clk(fosc/2 or fosc/4) tcc(r1) m u x m u x 1 0 m u x sync 2 cycles wdt
* this specification are subject to be changed without notice. EM78P154A/b 8-bit micro-controller for general purpose product 10 9.30.1997 *pull-down is not shown in the figure. fig. 6 the circuit of i/o port and i/o control register for port 5 *pull-high (down), open-drain are not shown in the figure. fig. 7(a) the circuit of i/o port and i/o control register for p60(/int)
11 * this specification are subject to be changed without notice. EM78P154A/b 8-bit micro-controller for general purpose product 9.30.1997 *pull-high (down), open-drain are not shown in the figure. fig. 7(b) the circuit of i/o port and i/o control register for p61~p67 fig. 7(c) block diagram of i/o port 6 with input change interrupt/wake-up iocf.1 vcc rf.1 ti 0 ti 1 ti 7
* this specification are subject to be changed without notice. EM78P154A/b 8-bit micro-controller for general purpose product 12 9.30.1997 usage of port 6 input change wake-up/interrupt (i) wake-up from port 6 input change (ii) port 6 input change interrupt (a) before sleep 1. read i/o port 6 (mov r6,r6) 1. disable wdt 2. execute "eni" 2. read i/o port 6 (mov r6,r6) 3. enable interrupt (set iocf.1) 3. execute "eni" or "disi" 4. if port 6 change (interrupt) 4. enable interrupt (set iocf.1) ? interrupt vector (008h) 5. execute slep instruction (b) after wake-up 1. if "eni" ? interrupt vector (008h) 2. if "disi" ? next instruction fig. 7(d) usage of port 6 input change wake-up/interrupt function * the rex is 430k ohm external resistor. fig. 8 the circuit of i/o port with r-option (p50,p51) reset and wake-up the reset can be caused by (1) power on reset, or voltage detector (2) reset pin input "low", or (3) wdt timeout (if enabled). note that only power on reset, or only voltage detector in case(1) is enabled in the system by code option bit . refer to fig. 9. the device will be kept in a reset condition for a period of approx. 18ms (one oscillator start-up timer period) after the reset is detected. once the reset occurs, the following functions are performed. ? the oscillator is running, or will be started. ? the program counter (r2) is set to all "0". ? all i/o port pins are configured as input mode (high-impedance state).
13 * this specification are subject to be changed without notice. EM78P154A/b 8-bit micro-controller for general purpose product 9.30.1997 ? the watchdog timer and prescaler are cleared. ? when power on, the upper 3 bits of r3 are cleared. ? the cont register is set to all "1" except the bit 6 (int flag). ? iocb register is set to all "1". ? iocc register is cleared. ? iocd register is set to all "1". ? bit 7 of ioce register is set to "1" and bits 4 and 6 of ioce are cleared. ? bits 0~2 of rf and bits 0~2 of iocf register are cleared. the sleep mode (power down mode) can be entered by executing the slep instruction. while entering sleep mode, the wdt (if enabled) is cleared but keeping running. the controller can be awakened by (1) external reset input on reset pin, (2) wdt time-out (if enabled), or (3) port 6 input change (if enabled). the two former cases will cause the controller reset. the t and p flags of r3 can be used to determine the source of the reset (wake-up). the last case is considered a continuation of program execution and the global interrupt (eni or disi being executed) decides whether or not the controller branches to the interrupt vector following wake-up. if eni instruction is executed before "slep", the instruction to be fetched is from 008h after wake- up. if disi instruction is executed before "slep", the instruction to be fetched is next instruction (the one after "slep" instruction) after wake-up. only one of the cases 2 and 3 can be enabled before entering sleep mode. that is, [a] if port 6 input change interrupt is enabled before "slep" instruction, the wdt must be disabled. hence, the controller can be awakened only by case 1 or 3. [b] if wdt is enabled before "slep" instruction, port 6 input change interrupt must be disabled. hence, the controller can be awakened only by case 1 or 2. refer to interrupt section. if port 6 input change interrupt is used to wake-up the controller (the case [a]), the following instructions must be executed before "slep". mov a, xx000110b ; select internal tcc clock contw clr r1 ; clear tcc and prescaler mov a, xxxx1110b ; select wdt and prescaler contw wdtc ; clear wdt and prescaler mov a, 0xxxxxxxb ; disable wdt iow re mov r6, r6 ; read port 6 mov a, 00000x1xb ; enable port 6 input interrupt iow rf eni (or disi) ; enable (or disable) global interrupt slep ; sleep nop one caution should be noted is that after wake-up from sleep mode, the wdt is enabled. the wdt operation (being enabled or disabled) should be appropriately controlled by software after wake-up from "slep".
* this specification are subject to be changed without notice. EM78P154A/b 8-bit micro-controller for general purpose product 14 9.30.1997 fig. 9 block diagram of reset of controller interrupt the em78p154 has interrupts which are falling edge triggered, as listed in following: (1) tcc timer overflow interrupt (2) port 6 input change interrupt (3) external interrupt (p60/int pin). before enabling port 6 input change interrupt, reading port 6 (e.g. mov r6,r6) is necessary. each pin of port 6 has the feature of interrupt on change. any pin configured as output is excluded from this feature. the port 6 interrupt can wake up the controller from sleep mode if interrupt is enabled prior to going into sleep mode by executing the "slep" instruction. when wake-up, the controller will continue to execute program in-line if global interrupt is disabled or branch to the interrupt vector 008h if global interrupt is enabled. rf is the interrupt status register which records the interrupt request in flag bit. iocf is the interrupt mask register. global interrupt is enabled by eni instruction and is disabled by disi instruction. when one of the interrupts (when enabled) generated, will cause the next instruction to be fetched from address 008h. once in the interrupt service routine the source of the interrupt can be determined by polling the flag bits in the rf register. the interrupt flag bit must be cleared in software before leaving the interrupt service routine and enabling interrupts to avoid recursive interrupts. the flag (except icif bit) in the interrupt status register (rf) is set regardless of the status of its mask bit or the execution of eni instruction. note that reading rf will get the output of logic and of rf and iocf. refer to fig. 10. the reti instruction exits interrupt routine and enables the global interrupt (execution of eni instruction). when an interrupt is generated by int instruction (when enabled), causes the next instruction to be fetched from address 001h. the locations of address 002h ~ 007h are reserved for special purpose (must be "nop"s).
15 * this specification are subject to be changed without notice. EM78P154A/b 8-bit micro-controller for general purpose product 9.30.1997 instruction set each instruction in the instruction set is a 13-bit word divided into an op code and one or more operands. normally, all instructions are executed within one single instruction cycle (one instruction consists of 2 oscillator periods), unless the program counter is changed by instruction mov r2,a, add r2,a, or instructions of arithmetic or logic operation on r2 (e.g. sub r2,a, bs (bc) r2,b, clr r2, ....). in this case, the execution takes two instruction cycles. under some condition, if the specification of the instruction cycle is not suitable for some applications, they can be modified as follows: (a) one instruction cycle consists of 4 oscillator periods. (b) jmp, call, ret, retl, reti, or the conditional skip (jbs, jbc, jz, jza, djz, djza) is tesed to be true are executed within two instruction cycles. the instructions that write to the program counter also take two instruction cycles. the case(a) is selected by the code option bit (clks). one instruction cycle consists of two oscillator clocks if clks bit is low, and consists of four oscillator clocks if clks bit is high. the case(b) is selected by the code option bit (cyes). the execution of those instructions listed in case (b) takes one instruction cycle if cyes bit is low, and takes two instruction cycles if cyes bit is high. case(a) and case(b) are independent options, that is, they can be selected individually. note that once 4 oscillator periods within one instruction cycle is selected in case(a), the internal clock source to tcc is clk=fosc/4 instead of fosc/ 2 that is shown in fig. 5. in addition, the instruction set has the following features: (1) every bit of any register can be set, cleared, or tested directly. (2) the i/o register can be regarded as general register. that is, the same instruction can operates on i/o register. the symbol r represents a register designator which specifies which one of the registers (including opera- tional registers and general purpose registers) is to be utilized by the instruction. b represents a bit field designator which selects the number of the bit, located in the register r, affected by the operation. fig. 10 interrupt input circuit
* this specification are subject to be changed without notice. EM78P154A/b 8-bit micro-controller for general purpose product 16 9.30.1997 k represents an 8 or 10-bit constant or literal value. instruction status binary hex hnemonic operation affected 0 0000 0000 0000 0000 nop no operation none 0 0000 0000 0001 0001 daa decimal adjust a c 0 0000 0000 0010 0002 contw a ? cont none 0 0000 0000 0011 0003 slep 0 ? wdt, stop oscillator t,p 0 0000 0000 0100 0004 wdtc 0 ? wdt t,p 0 0000 0000 rrrr 000r iow r a ? iocr none 0 0000 0001 0000 0010 eni enable interrupt none 0 0000 0001 0001 0011 disi disable interrupt none 0 0000 0001 0010 0012 ret [top of stack] ? pc none 0 0000 0001 0011 0013 reti [top of stack] ? pc, enable interrupt none 0 0000 0001 0100 0014 contr cont ? a none 0 0000 0001 rrrr 001r ior r iocr ? a none 0 0000 01rr rrrr 00rr mov r,a a ? r none 0 0000 1000 0000 0080 clra 0 ? az 0 0000 11rr rrrr 00rr clr r 0 ? rz 0 0001 00rr rrrr 01rr sub a,r r-a ? a z,c,dc 0 0001 01rr rrrr 01rr sub r,a r-a ? r z,c,dc 0 0001 10rr rrrr 01rr deca r r-1 ? az 0 0001 11rr rrrr 01rr dec r r-1 ? rz 0 0010 00rr rrrr 02rr or a,r a r ? az 0 0010 01rr rrrr 02rr or r,a a r ? rz 0 0010 10rr rrrr 02rr and a,r a & r ? az 0 0010 11rr rrrr 02rr and r,a a & r ? rz 0 0011 00rr rrrr 03rr xor a,r a ? r ? az 0 0011 01rr rrrr 03rr xor r,a a ? r ? rz 0 0011 10rr rrrr 03rr add a,r a + r ? a z,c,dc 0 0011 11rr rrrr 03rr add r,a a + r ? r z,c,dc 0 0100 00rr rrrr 04rr mov a,r r ? az 0 0100 01rr rrrr 04rr mov r,r r ? rz 0 0100 10rr rrrr 04rr coma r /r ? az 0 0100 11rr rrrr 04rr com r /r ? rz 0 0101 00rr rrrr 05rr inca r r+1 ? az 0 0101 01rr rrrr 05rr inc r r+1 ? rz 0 0101 10rr rrrr 05rr djza r r-1 ? a, skip if zero none 0 0101 11rr rrrr 05rr djz r r-1 ? r, skip if zero none 0 0110 00rr rrrr 06rr rrca r r(n) ? a(n-1) r(0) ? c, c ? a(7) c 0 0110 01rr rrrr 06rr rrc r r(n) ? r(n-1) r(0) ? c, c ? r(7) c 0 0110 10rr rrrr 06rr rlca r r(n) ? a(n+1) r(7) ? c, c ? a(0) c 0 0110 11rr rrrr 06rr rlc r r(n) ? r(n+1) r(7) ? c, c ? r(0) c 0 0111 00rr rrrr 07rr swapa r r(0-3) ? a(4-7) r(4-7) ? a(0-3) none
17 * this specification are subject to be changed without notice. EM78P154A/b 8-bit micro-controller for general purpose product 9.30.1997 instruction status binary hex hnemonic operation affected 0 0111 01rr rrrr 07rr swap r r(0-3) ? r(4-7) none 0 0111 10rr rrrr 07rr jza r r+1 ? a, skip if zero none 0 0111 11rr rrrr 07rr jz r r+1 ? r, skip if zero none 0 100b bbrr rrrr 0xxx bc r,b 0 ? r(b) none 0 101b bbrr rrrr 0xxx bs r,b 1 ? r(b) none 0 110b bbrr rrrr 0xxx jbc r,b if r(b)=0, skip none 0 111b bbrr rrrr 0xxx jbs r,b if r(b)=1, skip none 1 00kk kkkk kkkk 1kkk call k pc+1 ? [sp], (page, k) ? pc none 1 01kk kkkk kkkk 1kkk jmp k (page, k) ? pc none 1 1000 kkkk kkkk 18kk mov a,k k ? a none 1 1001 kkkk kkkk 19kk or a,k a k ? az 1 1010 kkkk kkkk 1akk and a,k a & k ? az 1 1011 kkkk kkkk 1bkk xor a,k a ? k ? az 1 1100 kkkk kkkk 1ckk retl k k ? a, [top of stack] ? pc none 1 1101 kkkk kkkk 1dkk sub a,k k-a ? a z,c,dc 1 1110 0000 0001 1e01 int pc+1 ? [sp], 001h ? pc none 1 1111 kkkk kkkk 1fkk add a,k k+a ? a z,c,dc code option register the em78p154 has one option register which is not part of the normal program memory. the option register cannot be accessed during normal program execution. 12 11 10 9 8 7 6~0 ms enwdtb clks cyes hlf hlp ------ bit 12 (ms): oscillator type selection 0: rc type 1: xtal type bit 11 (enwdtb): watchdog timer enable 0: enable 1: disable bit 10 (clks): clocks of each instruction cycle 0: two clocks 1: four clocks bit 9 (cyes): cycles of conditional skip instruction 0: one cycle 1: two cycles bit 8 (hlf): xtal frequency selection. 0: low frequency (32.768khz) 1: high frequency this bit is useful only when bit 12 (ms) is 1. when ms is 0, hlf must be 0. bit 7 (hlp): power consumption selection.(ref p19) 0: low power 1: high power this instruction can operate on ioc5~ioc6, iocb~iocf only. this instruction is not recommended to operate on rf. this instruction cannot operate on rf.
* this specification are subject to be changed without notice. EM78P154A/b 8-bit micro-controller for general purpose product 18 9.30.1997 bit 6~0 : not used. (default "00000001") security mode ------ security register the em78p154 has one security register which is not part of the normal program memory. the security register cannot be accessed during normal program execution. 12 11~0 /pt -------- bit 12 (/pt) : protect bit 0: protect enable 1: protect disable (user's program in otp-rom cannot be read through io0~io6) bit 11~0 : user's id code.
19 * this specification are subject to be changed without notice. EM78P154A/b 8-bit micro-controller for general purpose product 9.30.1997 oscillator the EM78P154A/b can be operated in there different oscillator options, three are rc type ' low xtal type ' high xtal type. the user can program three option bits (ms, hlf, hlp) to select one of these three modes. if ms=0 ' hlf=0 ' rc type oscillator is chosed and the frequency is determined by external rext ' cext which device can offer lots of cost saving in timing insensitive applications. if ms=1 ' hlf=0 ' hlp=0 ' low xtal type oscillator is chosed, in this case the oscillator is in low power and low frequency operation condition so the maxim frequency should not excess 4 mhz and you got the bonus of low current consumption. if ms=1 ' hlf=1 ' hlp=1 ' high xtal type oscillator is chosed, at this situation the oscillator is in high speed operation condition so the minum frequency should not less than 1mhz. because in this mode the current consumption is large than low power mode which in low frequency operation or battery environment should take into consideration. the typical operation speeds of crystal are listed below : conditions vdd (v) fxt max. (m) one cycles with two clocks 2.5 3.58 34 512 6.5 17 two cycles with two clocks 2.5 3.84 35 515 617 one cycles with four clocks 2.5 8 310 528 633 two cycles with foue clocks 2.5 9 311 531 636 n internal clock osc1 osc2/clkout fosc/4,2 v ss cext rext v dd
* this specification are subject to be changed without notice. EM78P154A/b 8-bit micro-controller for general purpose product 20 9.30.1997 cext rext average fosc @ 5v, 25 c average fosc @ 3v, 25 c 20pf 3.3k 3.20 mhz 2.47 mhz 5.1k 2.22 mhz 1.83 mhz 10k 1.28 mhz 1.14 mhz 100k 150 khz 143 khz 100pf 3.3k 1.13 mhz 974 khz 5.1k 758 khz 675 khz 10k 409 khz 376 khz 100k 51 khz 43.7 khz 300pf 3.3k 472 khz 420 khz 5.1k 310 khz 283 khz 10k 165 khz 153 khz 100k 17.5 khz 17.0 khz * measured on dip packages. in most case, the timing accuracy is not very important . so the "rc oscillator" offers lots of cost savings. but the rc oscillator frequency is a function of the supply voltage ' the resistor (rext) ' capacitor (cext) values and the operation temperature. in addition to this, the oscillator frequency will vary little from unit to unit due to process parameter variation. we strongly suggest user should take into account the frequency variation due to tolerance of rext ' cext values and the voltage temperature effect. besides, for more stable consideration, the cext should not less than 20pf and rext should not great than 1m ohm. in such case the pcb trace capacitance, package lead frame capacitance and leakage current will become frequency insensitive. if the rext become smaller the frequency become faster, however when rext value less the 1k ohm there may occure unstable condition due to the nmos can't discharge the capacitance's current correctly the user should pay attention on it. power on voltage detector the EM78P154A internal built-in power on voltage detector whichs detect level is set at 1.8 voltage. at some application you may find out your system would lost control after power on-off occured. in this circumstance we suggested strongly you should using the EM78P154A instead of em78p154b. no pains no gains, how ever using EM78P154A the internal power on voltage detector cost you 15 m a current consumption . so in some power consumption considerable application you should think about 15 m a pain.
21 * this specification are subject to be changed without notice. EM78P154A/b 8-bit micro-controller for general purpose product 9.30.1997 absolute maximum ratings items sym. condition rating temperature under bias t opr 0 c to 70 c storage temperature t str -65 c to 150 c input voltage v in -0.3v to +6.0v output voltage v o -0.3v to +6.0v dc electrical characteristic (t a =0 c ~ 70 c, v dd =5.0v 5%, v ss =0v) parameter sym. condition min. typ. max. unit supply oscillator crystal : vdd to 3v fxt one cycle with two clocks dc 4.0 mhz vdd to 5v dc 12.0 mhz rc : vdd to 5v f rc r : 5.0k w , c : 39pf f rc 20% 602 f rc 20% khz input leakage current i il1 v in = v dd , v ss 1 m a for input pins input high voltage v ih 2.0 v input low voltage v il 0.8 v input high threshold voltage v iht reset, tcc 2.0 v input low threshold voltage v ilt reset, tcc 0.8 v clock input high voltage v ihx osci 3.5 v clock input low voltage v ilx osci 1.5 v output high voltage v oh1 i oh = -10.0ma 2.4 v (port 5,6) output low voltage v ol1 i ol = 7.0ma 0.4 v (p50~p53,p60~p63,p66~p67) output low voltage v ol2 i ol = 10.0ma 0.4 v (p64,p65) pull-high current i ph pull-high active, input pin at v ss -50 -100 -240 m a pull-down current i pd pull-down active, input pin at v dd 25 50 120 m a power down current i sb all input and i/o pins at v dd , output 1 m a pin floating, wdt enabled operating supply current i cc1 reset='high', fosc=32khz(crystal (v dd =3v) type, clks="0"), output pin floating, 15 15 30 m a input pins at v dd , wdt disabled operating supply current i cc2 reset='high', fosc=32khz(crystal (v dd =3v) type,clks="0"), output pin floating, 20 35 m a input pins at v dd , wdt enabled operating supply current i cc3 reset='high', fosc=4mhz (crystal type,clks="0"), output pin floating 2 ma operating supply current i cc4 reset='high', fosc=12mhz (crystal type,clks="0"), output pin floating 4 ma
* this specification are subject to be changed without notice. EM78P154A/b 8-bit micro-controller for general purpose product 22 9.30.1997 * when the voltage of v dd rises between vop=0.7v and vdet, the output of voltage detector must be "low". voltage detector electrical characteristic (t a = 25 c) parameter symbol condition min. typ. max. unit detect voltage vdet v dd = 5v 1.6 1.8 2.0 v release voltage vrel v dd = 5v vdet x1.05 v current consumption iss v dd = 5v 20 m a operating voltage vop 0.7* 5.5 v temperature d vdet/ 0 c t 70 c -2 mv/ c characteristic of vdet d t a ac electrical characteristics (t a =0 c ~ 70 c, v dd =5.0v 5%, v ss =0v) input clk duty cycle dclk 45 50 55 % instruction cycle time tins xtal type 125 dc ns (clks="0") rc type 500 dc ns tcc input period ttcc note 1 (tins+20)/n ns device reset hold time tdr ta = 25 c18ms watchdog timer period twdt ta = 25 c18ms input pin setup time tset 0 ns input pin hold time thold 20 ns output pin delay time tdelay cload=20pf 50 ns note : n= selected prescaler ratio. parameter symbol condition min. typ. max. unit
23 * this specification are subject to be changed without notice. EM78P154A/b 8-bit micro-controller for general purpose product 9.30.1997 (clks="0") (clks="0")
* this specification are subject to be changed without notice. EM78P154A/b 8-bit micro-controller for general purpose product 24 9.30.1997 i/o pin timing ( clks="0") notes : clkout is available only in rc oscillator mode. tdelay thold tset p1 p2 p3 p4 p1 osco clkout i/o pin (input) i/o pin (output)

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